The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 19, 2021
Filed:
Aug. 01, 2018
Applicant:
Wuhan China Star Optoelectronics Technology Co., Ltd., Wuhan, CN;
Inventors:
Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1343 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); G02F 1/1333 (2006.01); G06F 3/041 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1288 (2013.01); G02F 1/13338 (2013.01); G02F 1/13439 (2013.01); G02F 1/133345 (2013.01); H01L 27/124 (2013.01); H01L 27/1222 (2013.01); H01L 27/1248 (2013.01); H01L 29/66757 (2013.01); H01L 29/78633 (2013.01); H01L 29/78675 (2013.01); G02F 2001/133357 (2013.01); G02F 2201/121 (2013.01); G02F 2201/123 (2013.01); G02F 2202/104 (2013.01); G06F 3/041 (2013.01); G06F 2203/04103 (2013.01);
Abstract
A manufacturing method of a display panel is provided and includes providing a substrate; and forming a buffer layer, a polysilicon layer, a gate electrode, an interlayer insulating layer, a first transparent electrode layer, a source electrode and drain electrode line, and a touch control line on the substrate in sequence. A masking process is omitted using a planarization layer as a photoresist layer of the interlayer insulating layer. One more masking process is omitted by forming the pixel electrode, the source electrode and drain electrode line and the touch control line in a same masking process.