The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 19, 2021

Filed:

Mar. 26, 2019
Applicant:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Inventor:

Wen-Yueh Jang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); H01L 27/11521 (2017.01); H01L 29/788 (2006.01); H01L 27/11558 (2017.01); H01L 27/11519 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 27/11519 (2013.01); H01L 27/11558 (2013.01); H01L 29/788 (2013.01);
Abstract

A memory structure and a manufacturing method thereof are provided. In the memory structure, a first dielectric layer is disposed on a substrate; a pair of gate stack structures is disposed on the first dielectric layer and each gate stack structure includes a word line, an erase gate and a second dielectric layer; a third dielectric layer is disposed on the surfaces of the gate stack structures; a pair of floating gates is disposed between the gate stack structures and located respectively on sidewalls of the gate stack structures, and top surfaces of the floating gates are lower than those of the erase gates; a fourth dielectric layer covers the first and third dielectric layers and the floating gates; a control gate is disposed on the fourth dielectric layer between the floating gates; and a doped region is disposed in the substrate beside the gate stack structures.


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