The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 19, 2021

Filed:

Apr. 27, 2018
Applicant:

Hs Elektronik Systeme Gmbh, Nördlingen, DE;

Inventors:

Richard Sinning, Schnelldorf, DE;

Bernd Loefflad, Nordlingen-Lopsingen, DE;

Markus Greither, Augsburg, DE;

Peter Brantl, Fremdingen, DE;

Josef Maier, Munningen, DE;

Rainer Seidel, Tussenhausen, DE;

Assignee:

HS ELEKTRONIK SYSTEM GMBH, Nordlingen, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/373 (2006.01); H01L 25/16 (2006.01); H01L 25/11 (2006.01); H01L 23/62 (2006.01); H01L 25/07 (2006.01); H01L 23/433 (2006.01); H01L 23/467 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3735 (2013.01); H01L 23/4334 (2013.01); H01L 23/467 (2013.01); H01L 23/62 (2013.01); H01L 25/071 (2013.01); H01L 25/074 (2013.01); H01L 25/117 (2013.01); H01L 25/16 (2013.01); H01L 23/367 (2013.01); H01L 24/48 (2013.01); H01L 2224/29111 (2013.01); H01L 2224/29139 (2013.01); H01L 2224/29144 (2013.01); H01L 2224/29147 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/12032 (2013.01); H01L 2924/1301 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/19105 (2013.01); H01L 2924/19106 (2013.01); H01L 2924/19107 (2013.01);
Abstract

The present invention relates to a power semiconductor chip module, comprising a substrate having a top side and a bottom side; at least one first power semiconductor device attached to the top side of the substrate; at least one first conductive structure thermally and electrically connecting the first power semiconductor device to the top side of the substrate; at least one second power semiconductor device attached to the bottom side of the substrate; and at least one second conductive structure connecting the second power semiconductor device to the bottom side of the substrate.


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