The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 19, 2021

Filed:

Jun. 09, 2015
Applicant:

Hitachi, Ltd., Tokyo, JP;

Inventors:

Takuya Okuyama, Tokyo, JP;

Masanao Yamaoka, Tokyo, JP;

Chihiro Yoshimura, Tokyo, JP;

Masato Hayashi, Tokyo, JP;

Akihito Akai, Tokyo, JP;

Assignee:

HITACHI, LTD., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/10 (2006.01); G06F 7/00 (2006.01); G06F 15/173 (2006.01); H04L 9/08 (2006.01); G06F 15/76 (2006.01); G06N 5/00 (2006.01); G06N 10/00 (2019.01);
U.S. Cl.
CPC ...
G06F 17/10 (2013.01); G06F 7/00 (2013.01); G06F 15/173 (2013.01); G06F 15/76 (2013.01); G06N 5/003 (2013.01); H04L 9/0852 (2013.01); G06N 10/00 (2019.01);
Abstract

An information processing apparatus manufactured at low cost and with ease and that is capable of making a search for a ground state of an arbitrary Ising model. An information processing unit containing a plurality of semiconductor chips, each retains a value of one spin or values of a plurality of spins and simulates interactions among the spins, inter-chip wiring between the necessary semiconductor chips, and a control unit that cause each semiconductor chip to perform interaction computation. The control unit converts data of a problem into data of a lattice-shaped Ising model, which is possibly expressed by the plurality of semiconductor chips, without causing a spin arrangement, in a ground state of an Ising model for the problem, to be changed. The data of the lattice-shaped Ising model is divided for allocation to the plurality of semiconductor chips, and causes each semiconductor chip to perform the interaction computation.


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