The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2021

Filed:

Nov. 29, 2017
Applicant:

Samsung Electro-mechanics Co., Ltd., Suwon-Si, KR;

Inventors:

Jong-Guk Kim, Suwon-si, KR;

Chul-Min Lee, Suwon-si, KR;

Sung-Jun Park, Suwon-si, KR;

Dong-Chul Shin, Suwon-si, KR;

Chang-Jae Lee, Suwon-si, KR;

Seon-Hye Kim, Suwon-si, KR;

Joong-Mo Hwang, Suwon-si, KR;

Sim-Hwan Park, Suwon-si, KR;

Myung-Gun Chong, Suwon-si, KR;

Tae-Wook Jung, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/06 (2006.01); H05K 3/00 (2006.01); H05K 3/40 (2006.01); H05K 1/03 (2006.01); H05K 1/09 (2006.01); H05K 3/38 (2006.01); H05K 3/18 (2006.01);
U.S. Cl.
CPC ...
H05K 3/06 (2013.01); H05K 1/0306 (2013.01); H05K 1/09 (2013.01); H05K 3/002 (2013.01); H05K 3/381 (2013.01); H05K 3/388 (2013.01); H05K 3/4038 (2013.01); H05K 3/181 (2013.01); H05K 2203/0361 (2013.01); H05K 2203/0376 (2013.01); H05K 2203/075 (2013.01); H05K 2203/0759 (2013.01); H05K 2203/0789 (2013.01);
Abstract

A manufacturing method for a printed circuit board includes: transferring roughness of a metal film to an insulating layer by laminating the metal film on the insulating layer, the metal film having the roughness formed on one surface thereof and having a discrete metal layer laminated thereon; exposing a surface of the insulating layer, on which the roughness is transferred, by removing the metal film; processing the surface of the insulating layer having the roughness formed thereon with an acidic solution; and forming a circuit pattern on the insulating layer by a plating process.


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