The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2021

Filed:

Sep. 03, 2019
Applicants:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Tokyo, JP;

Inventors:

Shigeto Fukatsu, Himeji Hyogo, JP;

Masaru Furukawa, Himeji Hyogo, JP;

Hiroshi Kono, Himeji Hyogo, JP;

Takuma Suzuki, Himeji Hyogo, JP;

Shunsuke Asaba, Himeji Hyogo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0256 (2006.01); H01L 21/02 (2006.01); H01L 21/00 (2006.01); H01L 21/336 (2006.01); H01L 29/16 (2006.01); H01L 29/78 (2006.01); H01L 29/51 (2006.01); H01L 21/76 (2006.01); H01L 29/66 (2006.01); H01L 51/05 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1608 (2013.01); H01L 21/7602 (2013.01); H01L 29/513 (2013.01); H01L 29/66053 (2013.01); H01L 29/7802 (2013.01); H01L 51/0529 (2013.01);
Abstract

A semiconductor device according to an embodiment includes a silicon carbide layer; a gate electrode; and a gate insulating layer which is provided between the silicon carbide layer and the gate electrode and includes a first silicon oxide layer and a second silicon oxide layer provided between the first silicon oxide layer and the gate electrode, the first silicon oxide layer having a first nitrogen concentration and a first thickness, the second silicon oxide layer having a second nitrogen concentration lower than the first nitrogen concentration and a second thickness. The second thickness between an end portion of the gate electrode and the silicon carbide layer is greater than the second thickness between a central portion of the gate electrode and the silicon carbide layer.


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