logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10892234 B1

PDFFull Text
Date of Patent:
Jan. 12, 2021

Filed:

Oct. 08, 2018

Method for detecting a differential fault analysis attack and a thinning of the substrate in an integrated circuit, and associated integrated circuit

Applicant:

Stmicroelectronics (Rousset) Sas, Rousset, FR;

Inventors:

Alexandre Sarafianos, Pourrieres, FR;

Abderrezak Marzaki, Aix en Provence, FR;

Assignee:

STMicroelectronics (Rousset) SAS, Rousset, FR;

Attorney:

Crowe & Dunlevy

Primary Examiner:

Taghi T Arani

Assistant Examiner:

Badri Champakesan

Int. Cl.
CPC ...
H01L 23/00 (2006.01); G06F 21/87 (2013.01); H04L 9/00 (2006.01); H01L 29/06 (2006.01); G06F 21/78 (2013.01); G06F 21/55 (2013.01);
U.S. Cl.
CPC ...
H01L 23/576 (2013.01); G06F 21/556 (2013.01); G06F 21/78 (2013.01); G06F 21/87 (2013.01); H01L 29/0646 (2013.01); H01L 29/0649 (2013.01); H04L 9/004 (2013.01); H04L 2209/12 (2013.01);
Abstract

An integrated circuit includes a semiconductor substrate having a rear face. A first semiconductor well within the substrate includes circuit components. A second semiconductor well within the substrate is insulated from the first semiconductor well and the rest of the substrate. The second semiconductor well provides a detection device that is configurable and designed, in a first configuration, to detect a thinning of the substrate via its rear face, and in a second configuration, to detect a DFA attack by fault injection into the integrated circuit.

Find Patent Forward Citations

Sarafianos, Alexandre. (2021). Method for detecting a differential fault analysis attack and a thinning of the substrate in an integrated circuit, and associated integrated circuit (U.S. Patent No. 10892234). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10892234

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…