The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2021

Filed:

Jul. 02, 2019
Applicant:

Lapis Semiconductor Co., Ltd., Yokohama, JP;

Inventors:

Osamu Koike, Yokohama, JP;

Yutaka Kadogawa, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 21/762 (2006.01); H01L 27/146 (2006.01); H01L 21/3105 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76898 (2013.01); H01L 21/76224 (2013.01); H01L 21/76819 (2013.01); H01L 23/481 (2013.01); H01L 21/31053 (2013.01); H01L 21/3212 (2013.01); H01L 21/76229 (2013.01); H01L 27/14636 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/13021 (2013.01); H01L 2224/13024 (2013.01); H01L 2225/06541 (2013.01);
Abstract

There is provided a semiconductor device comprising a semiconductor substrate having an active area in which a plurality of active elements are formed, and a non-active area excepting the active area; at least one electrode pad electrically connected to any of the active elements. At least one Through Silicon VIA electrode is formed, being electrically connected to the electrode pad by way of the non-active area. The non-active area has an insulating region obtained by forming an insulating film on the semiconductor substrate, and a dummy section obtained by leaving a base material of the semiconductor substrate in the insulating region. The dummy section is provided in a position where an outer edge of the Through Silicon VIA electrode does not intersect with the boundary between the insulating region and the dummy section.


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