The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2021

Filed:

Dec. 05, 2019
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Paul D. Kundarewich, Toronto, CA;

Grigor S. Gasparyan, San Jose, CA (US);

Mehrdad Eslami Dehkordi, Los Gatos, CA (US);

Guenter Stenz, Niwot, CO (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/333 (2020.01); G06F 30/392 (2020.01); G06F 30/327 (2020.01); G06F 111/04 (2020.01);
U.S. Cl.
CPC ...
G06F 30/333 (2020.01); G06F 30/327 (2020.01); G06F 30/392 (2020.01); G06F 2111/04 (2020.01);
Abstract

Disclosed approaches for processing a circuit design include providing access to checkpoint data of a design checkpoint of a circuit design and starting child processes by a parent process. An initial intermediate representation is generated by the parent process, and concurrent with the generating of the initial intermediate representation, the child processes load the checkpoint data into respective memory spaces. The parent process produces incremental updates to the design checkpoint. The parent process signals availability of the incremental updates to the child processes, which apply the incremental updates to the checkpoint data in the respective memory spaces. The child processes process the circuit design in response to completion of producing incremental updates by the parent placer process.


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