The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2021

Filed:

Apr. 20, 2015
Applicant:

Arm Ip Limited, Cambridge, GB;

Inventors:

Milosch Meriac, Cambridge, GB;

Hugo John Martin Vincent, Cambridge, GB;

James Crosby, Ely, GB;

Assignee:

ARM IP Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 21/74 (2013.01); G06F 12/14 (2006.01); G06F 9/46 (2006.01); G06F 9/54 (2006.01); G06F 21/60 (2013.01);
U.S. Cl.
CPC ...
G06F 9/45558 (2013.01); G06F 9/468 (2013.01); G06F 9/542 (2013.01); G06F 12/1441 (2013.01); G06F 21/602 (2013.01); G06F 21/74 (2013.01); G06F 2009/45587 (2013.01);
Abstract

A data processing system operates in a plurality of modes including a first privilege mode and a second privilege mode with the first privilege mode giving rights of access that are not available in the second privilege mode. Application code executes in the second privilege mode and generates function calls to hypervisor code which executes in the first privilege mode. These function calls are to perform a secure function requiring the rights of access which are only available in the first privilege mode. Scheduling code which executes in the second privilege mode controls scheduling of both the application code and the hypervisor code. Memory protection circuitry operating with physical addresses serves to control access permissions required to access different regions within the memory address space using configuration data which is written by the hypervisor code. The hypervisor code temporarily grants access to different regions within the physical memory address space to the system in the second privilege mode as needed to support the execution of code scheduled by the scheduling code.


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