The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2021

Filed:

Sep. 04, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

William Huott, Holmes, NY (US);

Yuen Chan, Poughkeepsie, NY (US);

Pradip Patel, Poughkeepsie, NY (US);

Daniel Rodko, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/3185 (2006.01); H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318541 (2013.01); G01R 31/31855 (2013.01); G01R 31/318572 (2013.01); G01R 31/318575 (2013.01); H03K 19/0016 (2013.01);
Abstract

Techniques for a power saving scannable latch output driver in an integrated circuit (IC) are described herein. An aspect includes receiving, by a circuit comprising a scannable latch, a scan signal. Another aspect includes, based on the scan signal being enabled, turning on a scan output driver of the scannable latch, wherein a scan input of the scannable latch propagates through the scannable latch to a scan output based on the scan output driver being turned on. Another aspect includes, based on the scan signal being disabled, turning off the scan output driver, wherein the scan output driver comprises a first p-type field effect transistor (PFET) and a first n-type field effect transistor (NFET), wherein a gate of the first PFET and a gate of the first NFET are connected to an output of a latch of the scannable latch.


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