The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2021

Filed:

Oct. 16, 2019
Applicant:

Analog Devices International Unlimited Company, Limerick, IE;

Inventors:

Abhishek Bandyopadhyay, Winchester, MA (US);

Akira Shikata, Everett, MA (US);

Keith Anthony O'Donoghue, Cork, IE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03M 3/00 (2006.01); H03M 1/00 (2006.01); H03M 1/12 (2006.01); H03M 1/80 (2006.01);
U.S. Cl.
CPC ...
H03M 3/37 (2013.01); H03M 3/422 (2013.01); H03M 3/464 (2013.01); H03M 3/496 (2013.01); H03M 1/001 (2013.01); H03M 1/06 (2013.01); H03M 1/12 (2013.01); H03M 1/804 (2013.01); H03M 3/30 (2013.01);
Abstract

Methods and devices are described for controlling excess loop delay (ELD) gain compensation in a digital-to-analog converter (DAC) of a successive approximation register (SAR) analog-to-digital converter (ADC) by using DAC unit elements in the ELD DAC and DACs for the SAR ADC efficiently. The ELD DAC and DAC partially share DAC units (e.g. capacitors or current sources) to minimize total DAC units used to limit area and power usage while maintaining operational flexibility. Different configurations provide ELD gains of less than or greater than one. A dedicated sampling capacitor is also provided to allow flexible gain control by capacitance ratio.


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