The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2021

Filed:

May. 20, 2019
Applicant:

Virginia Tech Intellectual Properties, Inc., Blacksburg, VA (US);

Inventors:

Nidhi Haryani, Blacksburg, VA (US);

Sungjae Ohn, Falls Church, VA (US);

Rolando Burgos, Blacksburg, VA (US);

Dushan Boroyevich, Blacksburg, VA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 7/538 (2007.01); H02M 7/5387 (2007.01); H02M 1/084 (2006.01);
U.S. Cl.
CPC ...
H02M 7/53871 (2013.01); H02M 1/084 (2013.01);
Abstract

A three-phase, N-level inverter and method are disclosed. A circuit topology of the inverter comprises first, second and third sets of switches and first, second and third inductors. Each switch comprises at least first, second and third terminals, the first terminals being control terminals. The first terminals of the first, second and third inductors are electrically coupled to the first, second and third sets of switches, respectively. A current controller performs a control algorithm that causes it to output first, second and third sets of gating signals to the control terminals of the switches of the first, second and third sets of switches, respectively, to cause them to be placed in an on state or an off state in a particular sequence to perform zero voltage switching while maintaining synchronization of the three phases of the three-phase, N-level inverter.


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