The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2021

Filed:

Nov. 19, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ashim Dutta, Menands, NY (US);

Ekmini Anuja de Silva, Singerlands, NY (US);

Jennifer Church, Troy, NY (US);

Luciana Meli Thompson, Albany, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 43/12 (2006.01); H01L 43/02 (2006.01); H01L 27/22 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 43/12 (2013.01); H01L 21/0217 (2013.01); H01L 21/02126 (2013.01); H01L 27/222 (2013.01); H01L 43/02 (2013.01); H01L 21/0228 (2013.01); H01L 21/02271 (2013.01); H01L 21/02274 (2013.01);
Abstract

A method for selectively encapsulating embedded memory pillars in a semiconductor device includes coating a passivation layer on a first dielectric surface on a first outer dielectric layer present in the semiconductor device. The passivation layer adheres to the dielectric surface selective to metal. The method includes depositing an encapsulation layer on side and top surfaces of the embedded memory pillars. The passivation layer prevents deposition of the encapsulation layer on the first dielectric surface of the first outer layer dielectric. The method includes removing the first outer dielectric layer from horizontal subraces around the embedded memory pillar and the encapsulation layer from the top surface of the embedded memory pillars.


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