The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2021

Filed:

Nov. 21, 2018
Applicant:

Osram Opto Semiconductors Gmbh, Regensburg, DE;

Inventors:

Reiner Windisch, Pettendorf, DE;

Florian Bösl, Regensburg, DE;

Andreas Dobner, Wenzenbach, DE;

Matthias Sperl, Mintraching, DE;

Assignee:

OSRAM OLED GmbH, Regensburg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/07 (2006.01); H01L 33/50 (2010.01); H01L 33/62 (2010.01); H01L 27/15 (2006.01); H01L 25/075 (2006.01); F21K 9/90 (2016.01); F21V 29/87 (2015.01); F21Y 115/10 (2016.01);
U.S. Cl.
CPC ...
H01L 25/0753 (2013.01); F21K 9/90 (2013.01); F21V 29/87 (2015.01); H01L 33/504 (2013.01); H01L 33/507 (2013.01); H01L 33/508 (2013.01); H01L 33/62 (2013.01); F21Y 2115/10 (2016.08); H01L 27/153 (2013.01); H01L 27/156 (2013.01); H01L 2933/005 (2013.01); H01L 2933/0033 (2013.01); H01L 2933/0041 (2013.01);
Abstract

An LED filament includes semiconductor chips arranged on a top side of a radiation-transmissive carrier, and at least partly covered with a radiation-transmissive first layer, the first layer and an underside of the carrier are covered with a second layer, phosphor is provided in the second layer, the phosphor is configured to shift a wavelength of the radiation of the semiconductor chip, no phosphor or phosphor including less than 50% of the concentration of the phosphor of the second layer is provided in the first layer, the carrier is formed from a further first layer and a carrier layer having cutouts, the carrier layer is arranged on the further first layer, the semiconductor chips are arranged on the further first layer in the regional of the cutouts of the carrier layer, and the first layer and the further first layer are at least partially covered with the second layer.


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