The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 2021
Filed:
Oct. 29, 2019
Applicant:
Commissariat a L'energie Atomique Aux Energies Alternatives, Paris, FR;
Inventors:
Stefan Landis, Grenoble, FR;
Hubert Teyssedre, Grenoble, FR;
Assignee:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/00 (2006.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H04L 9/32 (2006.01);
U.S. Cl.
CPC ...
H01L 23/57 (2013.01); H01L 21/0332 (2013.01); H01L 21/31144 (2013.01); H01L 21/76816 (2013.01); H01L 21/76847 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H04L 9/3278 (2013.01); H04L 2209/12 (2013.01);
Abstract
A method for securing an integrated circuit during the realization thereof, including the following steps: delimiting the integrated circuit into a first zone referred to as standard zone and into a second zone referred to as security zone, forming of a set of vias in the security zone, and introducing of a layer loaded with contaminant particles configured to randomly obstruct a portion of the vias, thus forming a random interconnection structure in the security zone, the random interconnection structure creating a physical unclonable function.