The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2021

Filed:

Aug. 29, 2019
Applicant:

Socionext Inc., Kanagawa, JP;

Inventors:

Chika Ito, Yokohama, JP;

Isaya Sobue, Yokohama, JP;

Assignee:

SOCIONEXT INC., Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 27/04 (2006.01); H03K 19/17736 (2020.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 27/0207 (2013.01); H01L 27/04 (2013.01); H03K 19/17744 (2013.01);
Abstract

For a semiconductor integrated circuit device in which IO cells are disposed, power supply voltage drop can be reduced using a multilayer interconnect. A power supply interconnect formed in a plurality of interconnect layers extends in an X direction that is a same direction as a direction in which the IO cells are aligned. In an area of a power supply IO cell, a power supply interconnect extending in a Y direction is disposed in one of the interconnect layers in which the power supply interconnect is not formed and an interconnect piece is disposed in a same position as a position of the power supply interconnect formed in an area of a signal IO cell in the Y direction at each of both ends of the area of the power supply IO cell in the X direction.


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