The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2021

Filed:

Jul. 24, 2019
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Houman Zahedmanesh, Heverlee, BE;

Victoria L. Calero Diaz Del Castillo, New York, NY (US);

Christian Witt, Overijse, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/76816 (2013.01); H01L 23/5283 (2013.01); H01L 23/53295 (2013.01);
Abstract

Example embodiments relate to interconnect structures and related methods. One embodiment includes an interconnect structure. The interconnect structure includes a first interconnection level including a first dielectric layer and a first set of conductive paths. The interconnect structure also includes a second interconnection level arranged above the first interconnection level and including a second dielectric layer and a second set of conductive paths. Further, the interconnect structure includes a third interconnection level arranged above the second interconnection level and including a third dielectric layer and a third set of conductive paths. In addition, the interconnect structure includes a fourth interconnection level arranged above the third interconnection level and including a fourth dielectric layer and a fourth set of conductive paths. Still further, the interconnect structure includes a first multi-level via structure and a second multi-level via structure.


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Zahedmanesh, Houman. (2021). Interconnect structure and related methods (U.S. Patent No. 10886215). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10886215

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