Multi-level hierarchical large block synthesis (hlbs) latch optimization

Abstract

A system to develop an integrated circuit includes a child placement module that places in a parent macro a child macro that contains therein a child logic circuit component. The parent macro has a first hierarchical level assigned thereto and the child macro has a lower second hierarchical level assigned thereto. The system further includes a timing analysis module and a component targeting module. The timing analysis module detects a timing fault in response to performing a first parent-level optimization process on the parent macro. The component targeting module extracts from the child macro a targeted logic circuit component and places the targeted logic circuit component in the parent macro. The timing analysis module performs a second parent-level optimization process on the parent macro that resolves the timing fault based on the placement of the targeted logic circuit component in the parent macro.