The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2021

Filed:

Apr. 19, 2019
Applicant:

Cisco Technology, Inc., San Jose, CA (US);

Inventors:

Tanjore K. Suresh, Fremont, CA (US);

David S. Walker, San Jose, CA (US);

Ravi Shankar Palagummi, San Jose, CA (US);

RaviKiran Kaidala Lakshman, San Jose, CA (US);

Kar Wai Kam, Fremont, CA (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01);
Abstract

In one embodiment, a direct memory access (DMA) controller within a host device obtains a packet to be processed by the host device, where the host device comprises a host processor, a network interface controller (NIC), and a co-processor of the NIC, and where the co-processor is configured to perform one or more specific packet processing operations. The DMA controller may then detect a DMA descriptor of the packet, and can determine, according to the DMA descriptor, how the packet is to be moved for processing within the host device. As such, the DMA controller may then move the packet, based on the determining, to one of either a host main memory, a NIC memory, or a co-processor memory of the host device.


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