The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2021

Filed:

Sep. 23, 2019
Applicant:

Morgan/weiss Technologies Inc., Beaverton, OR (US);

Inventors:

Morgan Johnson, Portland, OR (US);

Frederick G. Weiss, Newberg, OR (US);

Assignee:

MORGAN/WEISS TECHNOLOGIES INC., Beaverton, OR (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 7/00 (2006.01); G06F 13/16 (2006.01); H05K 1/02 (2006.01); H05K 1/18 (2006.01); H01L 23/32 (2006.01); G06F 1/32 (2019.01); H05K 1/11 (2006.01); H05K 1/14 (2006.01); G06F 13/40 (2006.01); G11C 5/04 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
G06F 13/16 (2013.01); G06F 1/32 (2013.01); G06F 13/4068 (2013.01); G11C 5/04 (2013.01); H01L 23/32 (2013.01); H01L 23/4985 (2013.01); H01L 23/49838 (2013.01); H05K 1/0237 (2013.01); H05K 1/0243 (2013.01); H05K 1/0296 (2013.01); H05K 1/111 (2013.01); H05K 1/115 (2013.01); H05K 1/147 (2013.01); H05K 1/181 (2013.01); H05K 1/189 (2013.01); H01L 2924/0002 (2013.01); H05K 1/141 (2013.01); H05K 7/00 (2013.01); H05K 2201/095 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/10189 (2013.01); H05K 2201/10378 (2013.01); H05K 2201/10515 (2013.01); H05K 2201/10522 (2013.01); Y02D 10/00 (2018.01); Y10T 29/4913 (2015.01);
Abstract

A computing device has a motherboard circuit substrate having at least a first layer of electrical interconnects, a socket arranged to receive a main processor for the computing device, the socket electrically coupled to at least a portion of the first layer of electrical interconnects, at least two interposer substrates between the main processor and the socket such that the interposer substrate electrically connects to the main processor and the socket, wherein the interposer substrate has a first set of interconnects that electrically connect between the socket and the first layer of electrical interconnects, at least two peripheral circuits on each interposer substrate, the peripheral circuit connected to the main processor through a second set of interconnects on the interposer substrate that connects to the main processor without connecting to the socket or the motherboard circuit substrate, wherein each interposer substrate is folded to allow each peripheral circuit to have an equal path length between the peripheral circuit and the main processor, wherein the at least two interposer substrates are stacked such that the at least two peripheral circuits on each interposer substrate are stacked with the at least two peripheral circuits on another of the at least two interposer substrates.


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