The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 2021
Filed:
Oct. 04, 2018
Microsoft Technology Licensing, Llc, Redmond, WA (US);
Henry Morgan, Redmond, WA (US);
Ten Tzen, Sammamish, WA (US);
Christopher Martin McKinsey, Sammamish, WA (US);
YongKang Zhu, Redmond, WA (US);
Terry Mahaffey, Apex, NC (US);
Pedro Miguel Sequeira de Justo Teixeira, Kirkland, WA (US);
Arun Upadhyaya Kishan, Kirkland, WA (US);
Youssef M. Barakat, Redmond, WA (US);
MICROSOFT TECHNOLOGY LICENSING, LLC, Redmond, WA (US);
Abstract
During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint. If so, the emulator emits machine code instruction(s) in the second ISA that perform the memory operation using a memory barrier.