The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2021

Filed:

Sep. 27, 2016
Applicant:

Upmem, Grenoble, FR;

Inventors:

Fabrice Devaux, La Conversion, CH;

Jean-François Roy, Grenoble, FR;

Assignee:

UPMEM, Grenoble, FR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 13/16 (2006.01); G06F 13/12 (2006.01); G06F 13/40 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06F 11/1068 (2013.01); G06F 13/128 (2013.01); G06F 13/1678 (2013.01); G06F 13/4018 (2013.01); G11C 29/52 (2013.01);
Abstract

A computer device comprises a first processor; a plurality of memory circuits, a first one of which comprises one or more other processors; a data bus coupling the first processor to each of the memory circuits, each of the memory circuits having a data port with a width of m bits and the data bus having a width of n bits, n being higher than m, the first processor and/or another circuit being suitable for reading or writing the data value of n bits in the first memory circuit by converting a first address into a plurality of second addresses corresponding to memory locations of m bits in the first memory circuit, and by performing the reading or writing operation of the data value of n bits in the first memory circuit over a plurality of memory access operations.


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