The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 05, 2021

Filed:

May. 01, 2018
Applicant:

Degirum Corporation, Menlo Park, CA (US);

Inventor:

Winston Lee, Palo Alto, CA (US);

Assignee:

DeGirum Corporation, Campbell, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/42 (2006.01); G06F 1/12 (2006.01);
U.S. Cl.
CPC ...
G06F 1/12 (2013.01); H04L 12/422 (2013.01);
Abstract

A cascaded clock ring network includes a clock path that transmits a source clock through series-connected processing nodes, from a first processing node to a last processing node. A data path transmits data through the processing nodes in response to the transmitted source clock, from the first processing node to the last processing node. The last processing node provides the transmitted source clock as an end clock signal, and provides the transmitted data as end data values. The end data values are written into a FIFO memory in response to the end clock signal. The end data values are subsequently read from the FIFO memory using the source clock signal, and are provided to the first processing node. A synchronizing circuit ensures that a plurality of end data values are initially written into the FIFO memory before an end data value is read from the FIFO memory.


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