The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 05, 2021
Filed:
Mar. 23, 2017
Applicant:
Agency for Science, Technology and Research, Singapore, SG;
Inventors:
Navab Singh, Singapore, SG;
Daw Don Cheam, Singapore, SG;
Assignee:
Agency for Science, Technology and Research, Singapore, SG;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); B81B 7/00 (2006.01); B81C 1/00 (2006.01); H01L 23/48 (2006.01); H01L 23/14 (2006.01); H01L 23/13 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
B81B 7/007 (2013.01); B81C 1/00301 (2013.01); B81C 1/00587 (2013.01); H01L 23/48 (2013.01); B81B 2203/033 (2013.01); B81B 2203/0315 (2013.01); B81B 2207/095 (2013.01); B81C 2201/014 (2013.01); B81C 2201/0132 (2013.01); B81C 2203/0118 (2013.01); H01L 21/486 (2013.01); H01L 23/13 (2013.01); H01L 23/147 (2013.01); H01L 23/49827 (2013.01);
Abstract
A through silicon interposer wafer and method of manufacturing the same. A through silicon interposer wafer having at least one cavity formed therein for MEMS applications and a method of manufacturing the same are provided. The through silicon interposer wafer includes one or more filled silicon vias formed sufficiently proximate to the at least one cavity to provide support for walls of the at least one cavity during subsequent processing of the interposer wafer.