The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Mar. 15, 2018
Applicant:

Sony Semiconductor Solutions Corporation, Kanagawa, JP;

Inventor:

Yoshiaki Tashiro, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/335 (2011.01); H04N 5/355 (2011.01); H04N 5/374 (2011.01); H04N 5/3745 (2011.01);
U.S. Cl.
CPC ...
H04N 5/35518 (2013.01); H04N 5/3741 (2013.01); H04N 5/37457 (2013.01);
Abstract

The present disclosure relates to a solid-state imaging device, an electronic apparatus, and a driving method for reducing power consumption of pixels, and achieving an increase in the number of pixels. Provided is a solid-state imaging device including a pixel array unit that includes pixels arranged in a matrix. From each of the pixels an output signal indicating a logarithmic characteristic is acquired. Each of the pixels includes: a photoelectric conversion unit; a reset transistor that resets the photoelectric conversion unit in accordance with a reset signal; a first amplification transistor that amplifies a signal received from the photoelectric conversion unit; a selection transistor that selects a signal received from the first amplification transistor in accordance with a selection signal; a second amplification transistor that amplifies a signal received from the selection transistor, and applies the amplified signal to a vertical signal line; and a bias transistor that functions as a current source. The first amplification transistor and the second amplification transistor are each connected to a power source voltage. For example, the technology according to the present disclosure is applicable to a logarithmic sensor in a solar cell mode.


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