The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Nov. 27, 2019
Applicant:

Aviat U.s., Inc., Austin, TX (US);

Inventors:

Sergio Licardie, Cupertino, CA (US);

Rishipal Arya, San Jose, CA (US);

Robert Brown, Boulder Creek, CA (US);

Assignee:

Aviat U.S., Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 1/00 (2006.01); H04B 7/08 (2006.01); H03M 13/37 (2006.01); H03M 13/47 (2006.01); H04L 1/02 (2006.01); H04B 7/10 (2017.01); H03M 13/45 (2006.01); H03M 13/00 (2006.01); H03M 13/09 (2006.01);
U.S. Cl.
CPC ...
H04L 1/0061 (2013.01); H03M 13/37 (2013.01); H03M 13/451 (2013.01); H03M 13/47 (2013.01); H03M 13/6306 (2013.01); H04B 7/0882 (2013.01); H03M 13/09 (2013.01); H04B 7/10 (2013.01); H04L 1/0045 (2013.01); H04L 1/02 (2013.01);
Abstract

A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.


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