The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 2020
Filed:
Apr. 07, 2020
Samsung Electronics Co., Ltd., Suwon-si, KR;
Jaehong Jung, Bucheon-si, KR;
Sangdon Jung, Yongin-si, KR;
Seunghyun Oh, Seoul, KR;
Kyungmin Lee, Yongin-si, KR;
SAMSUNG ELECTRONICS CO.. LTD., Suwon-si, KR;
Abstract
A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator configured to generate an output clock, and a sub-sampling PLL circuit configured to receive, from the voltage-controlled oscillator, the generated output clock as feedback, and perform a phase-locking operation on the received output clock. The sub-sampling PLL circuit includes a buffer configured to buffer the received output clock, and the sub-sampling PLL circuit is further configured to adaptively adjust an internal signal to maintain a loop bandwidth of the sub-sampling PLL circuit, based on a change of a characteristic of the buffer according to at least one of process, voltage, and temperature (PVT) change.