The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Jul. 01, 2019
Applicant:

Marvell International Ltd., Hamilton, BM;

Inventors:

Manisha Gambhir, Cupertino, CA (US);

Ahmed Hesham Mostafa, San Jose, CA (US);

Myung Jae Yoo, Sunnyvale, CA (US);

Zubir Adal, Union City, CA (US);

Assignee:

MARVELL ASIA PTE, LTD., Singapore, SG;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/099 (2006.01); H03L 7/093 (2006.01); H03L 7/095 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0992 (2013.01); H03L 7/093 (2013.01); H03L 7/095 (2013.01);
Abstract

A method includes receiving data for a desired output frequency of an output clock of a phase locked loop (PLL) circuit. The method includes determining a preset value for a digitally controlled oscillator (DCO) of the PLL circuit, determining first gain coefficients and second gain coefficients for a filter of the PLL circuit, and determining ratio values for a divider circuit of the PLL circuit based on the data. The method includes providing the preset value to the DCO, the first gain coefficients to the filter, and the ratio values to the divider circuit while the PLL circuit operates in an open-loop configuration. The method includes subsequently operating the PLL circuit in a closed-loop configuration by connecting the filter to the DCO, and providing the second gain coefficients to the filter in response to detecting a phase lock of the PLL circuit operating in the closed-loop configuration.


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