The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Mar. 26, 2018
Applicant:

Semiconductor Components Industries, Llc, Phoenix, AZ (US);

Inventors:

Kinam Song, Seoul, KR;

JunHo Lee, Bucheon, KR;

Wonhi Oh, Bucheon, KR;

Jinkyu Choi, Bucheon, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/08 (2006.01); H03K 5/01 (2006.01); H03K 19/003 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 17/08 (2013.01); H03K 5/01 (2013.01); H03K 19/003 (2013.01); H03K 2005/00078 (2013.01); H03K 2217/0063 (2013.01); H03K 2217/0072 (2013.01);
Abstract

A circuit for controlling a gate driver includes a delay circuit, a first logic circuit, and a second logic circuit. The delay circuit receives a first turn-off signal and produces a second turn-off signal by delaying an assertion of the first turn-off signal by a freewheeling duration. The first logic circuit receives the first and second turn-off signals and produces a smart turn-off signal by asserting the smart turn-off signal when the first turn-off signal is asserted and the second turn-off signal is not asserted. The second logic circuit receives a restart signal and the smart turn-off signal and produces a smart reset signal by asserting the smart reset signal when the restart signal and the smart turn-off signal are de-asserted, and de-asserting the smart reset signal when one or more of the restart signal and the smart turn-off signal are asserted.


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