The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Jun. 28, 2019
Applicant:

Sharp Kabushiki Kaisha, Sakai, JP;

Inventor:

Hidenobu Kimoto, Sakai, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 21/465 (2006.01); H01L 29/26 (2006.01); H01L 21/4763 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1225 (2013.01); H01L 21/465 (2013.01); H01L 21/47635 (2013.01); H01L 27/124 (2013.01); H01L 27/1259 (2013.01); H01L 29/26 (2013.01); H01L 29/45 (2013.01); H01L 29/7869 (2013.01);
Abstract

An active matrix substrate includes a thin film transistor having a gate electrode, an oxide semiconductor layer disposed on the gate electrode via a gate insulating layer, and a source electrode and a drain electrode disposed on the oxide semiconductor layer. A plurality of gate bus lines and the gate electrode are made of a first electrically conductive film. At least part of each of the plurality of source bus lines, the source electrode, and the drain electrode have a multilayer structure including a lower layer that is made of a second electrically conductive film and an upper layer that is made of a first transparent electrically conductive film. Between the plurality of source bus lines and the gate insulating layer, a plurality of first oxide strips extending along the first direction are disposed, the first oxide strips being made of the same oxide semiconductor film as the oxide semiconductor layer. Each of the plurality of source bus lines is located on an upper face of the corresponding first oxide strip, and a width of each of the plurality of source bus lines along a second direction is smaller than a width of one corresponding first oxide strip along the second direction.


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