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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10879260 B1

PDFFull Text
Date of Patent:
Dec. 29, 2020

Filed:

Feb. 28, 2019

Bonded assembly of a support die and plural memory dies containing laterally shifted vertical interconnections and methods for making the same

Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Tatsuya Uryu, Yokkaichi, JP;

Satoshi Shimizu, Yokkaichi, JP;

Nobuyuki Fujimura, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:

The Marbury Law Group PLLC

Primary Examiner:

Calvin Y Choi

Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 27/11582 (2017.01); H01L 25/065 (2006.01); G11C 5/06 (2006.01); G11C 16/08 (2006.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 27/11558 (2017.01); H01L 27/1157 (2017.01); H01L 27/11573 (2017.01); H01L 27/11529 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 5/063 (2013.01); G11C 16/08 (2013.01); H01L 25/0657 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11556 (2013.01); H01L 27/11558 (2013.01); H01L 27/11573 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06541 (2013.01);
Abstract

A bonded assembly includes a first memory die containing a first three-dimensional memory device, a second memory die containing a second three-dimensional memory device, and a support die bonded to the first memory die and comprising a peripheral circuitry configured to control the first three-dimensional memory device and the second three-dimensional memory device. The first memory die includes multiple rows of first-die proximal bonding pads, multiple rows of first-die distal bonding pads, and a plurality of first-die laterally-shifting electrically conductive paths connecting a respective one of the first-die proximal bonding pads and a respective one of the first-die distal bonding pads that is laterally offset from the respective one of the first-die proximal bonding pads. The first memory die and the second memory die can have an identical layout, and electrical connections can be shifted through the first memory die by the offset distance.

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