The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 2020
Filed:
Sep. 02, 2016
Applicant:
Sony Corporation, Tokyo, JP;
Inventor:
Naoki Saka, Kanagawa, JP;
Assignee:
Sony Corporation, Toyko, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 21/84 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H01L 23/66 (2006.01); H01L 27/12 (2006.01); H01L 23/485 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5225 (2013.01); H01L 21/7682 (2013.01); H01L 21/76895 (2013.01); H01L 21/84 (2013.01); H01L 23/528 (2013.01); H01L 23/5222 (2013.01); H01L 23/535 (2013.01); H01L 23/53295 (2013.01); H01L 23/66 (2013.01); H01L 27/1203 (2013.01); H01L 23/485 (2013.01);
Abstract
A semiconductor device in which the generation of a distortion of a signal is suppressed, and a method for manufacturing the semiconductor device are disclosed. The semiconductor device includes a transistor region in which a field effect transistor is provided; and an interconnection region in which a metal layer electrically connected to the field effect transistor is provided. The interconnection region includes an insulating layer provided between the metal layer and a substrate, and a low-permittivity layer provided in the insulating layer below the metal layer and having a lower permittivity than the insulating layer.