The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 2020
Filed:
Sep. 23, 2019
Infineon Technologies Ag, Neubiberg, DE;
Reinhold Bayerer, Reichelsheim, DE;
Frank Sauerland, Werne, DE;
Infineon Technologies AG, Neubiberg, DE;
Abstract
A power semiconductor module arrangement includes a semiconductor substrate having first and second metallization layers attached to a dielectric insulation layer, the dielectric insulation layer being disposed between the metallization layers. A layer of heat-conducting material is arranged between the semiconductor substrate and a base plate in a vertical direction of the power semiconductor module arrangement. The layer of heat-conducting material is arranged adjacent to a plane surface of the semiconductor substrate and adjacent to a plane surface of the base plate. The semiconductor substrate has a first thermal expansion coefficient of 8 ppm/K or lower, the base plate has a second thermal expansion coefficient of 9 ppm/K or lower, and the layer of heat-conducting material has a third thermal expansion coefficient of 18 ppm/K or higher. The layer of heat-conducting material has a thickness in the vertical direction of between 40 μm and 150 μm.