The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 2020
Filed:
Apr. 02, 2019
Applicant:
Rohm Co., Ltd., Kyoto, JP;
Inventor:
Hideaki Yanagida, Kyoto, JP;
Assignee:
ROHM CO., LTD., Kyoto, JP;
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 23/13 (2006.01); H01L 21/56 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3135 (2013.01); H01L 21/481 (2013.01); H01L 21/4853 (2013.01); H01L 21/561 (2013.01); H01L 23/13 (2013.01); H01L 23/49811 (2013.01); H01L 23/49838 (2013.01); H01L 23/5386 (2013.01); H01L 24/08 (2013.01); H01L 2224/08225 (2013.01);
Abstract
An electronic component includes a substrate which has a first major surface on one side and a second major surface on the other side, a chip which has a mounting surface on one side and a non-mounting surface on the other side and is disposed on the first major surface of the substrate in a posture that the mounting surface faces the first major surface of the substrate, a sealing insulation layer which seals the chip so as to expose the non-mounting surface above the first major surface of the substrate, and a cover layer which covers the non-mounting surface of the chip.