The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Mar. 04, 2019
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Ryo Sekiguchi, Tokyo, JP;

Shingo Yanagawa, Kanagawa, JP;

Yasuhiko Kurosawa, Kanagawa, JP;

Eriko Akaihata, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5642 (2013.01); G11C 11/5628 (2013.01); G11C 13/004 (2013.01); G11C 16/34 (2013.01);
Abstract

A memory system includes a first memory, a second memory, and a first circuit. The first memory includes a memory cell array including memory cell transistors, and a peripheral circuit configured to read data of a plurality of bits stored in a memory cell transistor of the memory cell array based on a comparison between threshold voltages of the memory cell transistor and at least a part of n determination voltages (n≥3). The first circuit is configured to calculate an estimated value of each of n−m determination voltages based on values of m determination voltages (2≤m≤n−1) among the n determination voltages, and calculate a difference between a value of each of the n−m determination voltages and a corresponding estimated value. The second memory is configured to store values of the m determination voltages and the difference for each of the n−m determination voltages.


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