The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Jun. 04, 2019
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Vianney Antoine Choserot, Antibes, FR;

Andy Wangkun Chen, Austin, TX (US);

Sriram Thyagarajan, Austin, TX (US);

Yew Keong Chong, Austin, TX (US);

Munish Kumar, Noida, IN;

Assignee:

Arm Limited, Cambridge, GB;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 11/418 (2006.01); H01L 27/11 (2006.01); G11C 11/56 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 11/412 (2013.01); G11C 11/418 (2013.01); G11C 11/56 (2013.01); H01L 27/1104 (2013.01);
Abstract

Various implementations described herein are directed to memory circuitry having an array of bitcells and bitlines coupled to columns of the bitcells. Also, column decoder circuitry may be coupled to the bitcells via the bitlines, and the column decoder circuitry may have read logic coupled to an output node. The column decoder circuitry may have select logic coupled between a voltage supply and the read logic. Enable signals may be used to activate the select logic to pass the voltage supply to the read logic, and the bitlines provide bitline signals that activate the read logic to pass the voltage supply from the select logic to the output node.


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