The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Jul. 03, 2019
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Zhiyong Wang, Cupertino, CA (US);

Kai Zhu, Palo Alto, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01);
Abstract

Disclosed approaches for pipelining signal paths in an integrated circuit (IC) device include receiving by a design tool a circuit design to be implemented in the integrated circuit device. The design tool identifies signals of the circuit design that require pipeline registers between drivers and loads of the signals, and relaxes an initial timing requirement to a relaxed timing requirement. The design tool determines respective numbers of pipeline registers to insert between each driver and load of each of the signals based on the relaxed timing requirement. The design tool inserts in the circuit design, respective sets of the respective numbers of pipeline registers between each driver and load of each of the signals. The design tool places the respective sets of the pipeline registers on the IC device using the initial timing requirement.


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