The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Apr. 27, 2018
Applicants:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Stmicroelectronics Application Gmbh, Ascheim-Dornach, DE;

Inventors:

Roberto Colombo, Munich, DE;

Nicolas Bernard Grossier, Oreno di Vimercate, IT;

Giovanni Disirio, Salerno, IT;

Lorenzo Re Fiorentin, Turin, IT;

Assignees:

STMICROELECTRONICS S.R.L., Agrate Brianza, IT;

STMICROELECTRONICS APPLICATION GMBH, Ascheim-Dornach, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/71 (2013.01); H04L 9/06 (2006.01); G06F 11/07 (2006.01); G06F 21/57 (2013.01); G06F 21/60 (2013.01); G06F 21/72 (2013.01); G06F 21/77 (2013.01); H03K 19/17728 (2020.01);
U.S. Cl.
CPC ...
G06F 21/71 (2013.01); G06F 11/0721 (2013.01); G06F 11/0751 (2013.01); G06F 11/0772 (2013.01); G06F 21/57 (2013.01); G06F 21/602 (2013.01); G06F 21/72 (2013.01); G06F 21/77 (2013.01); H03K 19/17728 (2013.01); H04L 9/0618 (2013.01); H04L 2209/12 (2013.01); H04L 2209/127 (2013.01);
Abstract

A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.


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