The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Aug. 27, 2018
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Luke Yen, Redmond, WA (US);

Niket Choudhary, Bangalore, IN;

Pritha Ghoshal, Raleigh, NC (US);

Thomas Philip Speier, Wake Forest, NC (US);

Brian Michael Stempel, Raleigh, NC (US);

William James McAvoy, Raleigh, NC (US);

Patrick Eibl, Durham, NC (US);

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0871 (2016.01); G06F 3/06 (2006.01); G06F 12/0862 (2016.01); G06F 12/0815 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0871 (2013.01); G06F 3/0611 (2013.01); G06F 3/0631 (2013.01); G06F 3/0656 (2013.01); G06F 3/0673 (2013.01); G06F 12/0815 (2013.01); G06F 12/0862 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/604 (2013.01);
Abstract

A method, apparatus, and system for prefetching exclusive cache coherence state for store instructions is disclosed. An apparatus may comprise a cache and a gather buffer coupled to the cache. The gather buffer may be configured to store a plurality of cache lines, each cache line of the plurality of cache lines associated with a store instruction. The gather buffer may be further configured to determine whether a first cache line associated with a first store instruction should be allocated in the cache. If the first cache line associated with the first store instruction is to be allocated in the cache, the gather buffer is configured to issue a pre-write request to acquire exclusive cache coherency state to the first cache line associated with the first store instruction.


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