The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2020

Filed:

May. 02, 2019
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Cristian Marcu, San Jose, CA (US);

Feng Zhao, San Jose, CA (US);

Wei Deng, San Jose, CA (US);

Chunwei Chang, San Jose, CA (US);

Robert K. Kong, San Francisco, CA (US);

Saeed Chehrazi, Irvine, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01); H03L 7/18 (2006.01); H03L 7/099 (2006.01); H03L 7/093 (2006.01); H03L 7/089 (2006.01);
U.S. Cl.
CPC ...
H03L 7/18 (2013.01); H03L 7/0891 (2013.01); H03L 7/093 (2013.01); H03L 7/099 (2013.01);
Abstract

In a computer system, a phase-locked loop circuit may generate a clock signal using a reference signal. The phase-locked loop circuit may include a programmable divider stage that includes multiple divider stages. When a frequency calibration is initiated on the phase-locked loop circuit, a control circuit may generate a pause signal in response to one or more of the divider stages reaching a particular logic state. The programmable divider stage may hold the one or more of the divider stages in the particular logic state using the pause signal.


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