The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 2020
Filed:
Oct. 20, 2006
Applicant:
Ashay Chitnis, Goleta, CA (US);
Inventor:
Ashay Chitnis, Goleta, CA (US);
Assignee:
Cree, Inc., Goleta, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 33/38 (2010.01); H01L 33/00 (2010.01); H01L 33/64 (2010.01);
U.S. Cl.
CPC ...
H01L 33/0093 (2020.05); H01L 23/481 (2013.01); H01L 33/382 (2013.01); H01L 33/64 (2013.01);
Abstract
A method for fabricating semiconductor devices at the wafer level, and devices fabricated using the method, are described. Wafer-level bonding using a relatively thick layer of electrically conducting bond medium was used to achieve void-free permanent wafer level bonding. The bond medium can be introduced to the pre-bonded wafers by deposition or as a preform. The invention provides a low cost, simple and reliable wafer bonding technology which can be used in a variety of device fabrication processes, including flip chip packaging.