The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 2020
Filed:
Oct. 18, 2019
Alta Devices, Inc., Sunnyvale, CA (US);
Nikhil Jain, Sunnyvale, CA (US);
Andrew J. Ritenour, San Jose, CA (US);
Ileana Rau, Cupertino, CA (US);
Claudio Canizares, Morgan Hill, CA (US);
Lori D. Washington, Union City, CA (US);
Gang He, Cupertino, CA (US);
Brendan M. Kayes, Los Gatos, CA (US);
ALTA DEVICES, INC., Sunnyvale, CA (US);
Abstract
A growth structure having a lattice transition (or graded buffer) or an engineered growth structure with a desired lattice constant, different from a lattice constant of conventional substrates like GaAs, Si, Ge, InP, under a release layer or an etch stop layer is used as a seed crystal for growing optoelectronic devices. The optoelectronic device can be a photovoltaic device having one or more subcells (e.g., lattice-matched or lattice-mismatched subcells). The release layer can be removed using different processes to separate the optoelectronic device from the growth structure, which may be reused, or from the engineered growth structure. When using the etch stop layer, the growth structure or the engineered growth structure may be grinded or etched away. The engineered growth structure may be made from a layer transfer process between two wafers or from a ternary and/or a quaternary material. Methods for making the optoelectronic device are also described.