The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2020

Filed:

Sep. 19, 2018
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Ordos Yuansheng Optoelectronics Co., Ltd., Inner Mongolia, CN;

Inventors:

Jinjin Xue, Beijing, CN;

Dawei Shi, Beijing, CN;

Haifeng Xu, Beijing, CN;

Lu Yang, Beijing, CN;

Wentao Wang, Beijing, CN;

Lei Yan, Beijing, CN;

Lei Yao, Beijing, CN;

Fang Yan, Beijing, CN;

Xiaowen Si, Beijing, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/12 (2006.01); G02F 1/1362 (2006.01); G02F 1/1343 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78696 (2013.01); G02F 1/134309 (2013.01); G02F 1/136286 (2013.01); H01L 27/124 (2013.01); H01L 27/127 (2013.01); H01L 27/1225 (2013.01); H01L 27/1251 (2013.01); H01L 29/78633 (2013.01); H01L 29/78645 (2013.01); G02F 2201/121 (2013.01); G02F 2201/123 (2013.01); H01L 29/0692 (2013.01);
Abstract

A thin-film transistor (TFT), an array substrate, a manufacturing method thereof and a display device are provided. The TFT includes an active layer, a gate electrode, a first source/drain electrode and a second source/drain electrode. The active layer includes a first channel region and a second channel region, a first source/drain area between the first channel region and the second channel region, and a second source/drain area opposite to the first source/drain area through the first channel region or the second channel region. The gate electrode includes a first gate electrode and a second gate electrode which are respectively overlapped with the first channel region and the second channel region. The first source/drain electrode and the second source/drain electrode are respectively electrically connected with the first source/drain area and the second source/drain area of the active layer.


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