The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2020

Filed:

May. 26, 2017
Applicant:

Shindengen Electric Manufacturing Co., Ltd., Tokyo, JP;

Inventors:

Daisuke Arai, Saitama, JP;

Mizue Kitada, Saitama, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H02M 3/156 (2006.01); H02M 7/537 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0634 (2013.01); H01L 29/0688 (2013.01); H01L 29/1095 (2013.01); H01L 29/7813 (2013.01); H02M 3/156 (2013.01); H02M 7/537 (2013.01); H01L 29/1608 (2013.01);
Abstract

A MOSFET according to the present invention includes a semiconductor base substrate having a super junction structure. A gate electrode is on a first main surface side of the semiconductor base substrate by way of a gate insulation film, wherein in a state where a total amount of dopant in an n-type column region differs from a total amount of dopant in a p-type column region, assuming a depth position where an average positive charge density ρ(x) becomes 0 as X', assuming a deepest depth position of the surface of the depletion layer on the first main surface side as X′, assuming a depth position where the reference average positive charge density ρ(x) becomes 0 as X, and assuming a deepest depth position of the depletion layer on the first main surface side as X, a relationship of |X−X′|<|X−X′| is satisfied.


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