The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2020

Filed:

Aug. 27, 2019
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Toshifumi Watanabe, Yokohama Kanagawa, JP;

Naofumi Abiko, Kawasaki Kanagawa, JP;

Mario Sako, Yokohama Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/26 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 7/08 (2006.01); G11C 16/30 (2006.01); G11C 16/34 (2006.01); G11C 16/24 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 7/08 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/30 (2013.01); G11C 16/3459 (2013.01);
Abstract

A semiconductor memory cell includes a memory cell, a word line and a source line both connected to the memory cell, and a control circuit. During a read operation on the memory cell, the control circuit applies a first voltage to the word line, applies a second voltage greater than the first voltage to the word line, and then applies a third voltage which is greater than the first voltage and smaller than the second voltage to the word line. During the read operation on the memory cell, the control circuit also applies a fourth voltage to the source line according to a timing at which the second voltage is applied to the word line, and then applies a fifth voltage smaller than the fourth voltage to the source line.


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