The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 22, 2020
Filed:
Dec. 31, 2019
Applicant:
SK Hynix Inc., Icheon-si Gyeonggi-do, KR;
Inventors:
Geun Ho Choi, Icheon-si Gyeonggi-do, KR;
Kyung Mook Kim, Icheon-si Gyeonggi-do, KR;
Woongrae Kim, Icheon-si Gyeonggi-do, KR;
Assignee:
SK hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 7/22 (2006.01); G11C 7/10 (2006.01); G11C 8/06 (2006.01); G11C 29/18 (2006.01); G11C 29/12 (2006.01); G11C 29/14 (2006.01); G11C 8/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/22 (2013.01); G11C 7/1051 (2013.01); G11C 8/06 (2013.01); G11C 8/10 (2013.01); G11C 29/12015 (2013.01); G11C 29/14 (2013.01); G11C 29/18 (2013.01);
Abstract
A semiconductor device includes a variable delay circuit and an address latch circuit. The variable delay circuit delays a read signal by a delay time to generate a latch control signal during an initialization operation and receives a feedback signal to adjust the delay time for delaying the read signal during the initialization operation. The address latch circuit detects a logic level of a transfer address when the latch control signal is inputted to the address latch circuit and generates the feedback signal.