The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2020

Filed:

Sep. 06, 2019
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Anthony P. DeLaurier, Los Altos, CA (US);

Michael J. Swift, Brooklyn, NY (US);

Michal Valient, San Jose, CA (US);

Robert S. Hartog, Windermere, CA (US);

Tyson J. Bergland, Sunnyvale, CA (US);

Gokhan Avkarogullari, San Jose, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 15/04 (2011.01); G06F 12/1009 (2016.01); G06T 1/60 (2006.01); G06F 9/38 (2018.01); G06T 15/00 (2011.01); G06F 12/0811 (2016.01); G06F 9/50 (2006.01); G06T 11/00 (2006.01);
U.S. Cl.
CPC ...
G06T 15/04 (2013.01); G06F 9/3877 (2013.01); G06F 9/5016 (2013.01); G06F 12/0811 (2013.01); G06F 12/1009 (2013.01); G06T 1/60 (2013.01); G06T 11/001 (2013.01); G06T 15/005 (2013.01);
Abstract

Techniques are disclosed relating to memory allocation for graphics surfaces. In some embodiments, graphics processing circuitry is configured to access a graphics surface based on an address in a surface space assigned to the graphics surface. In some embodiments, first translation circuitry is configured to access one or more entries in a set of multiple translation entries for pages of the surface space (where the translation entries are stored using addresses in a virtual space and map pages of the surface space to the virtual space) and translate address information for the surface space to address information in the virtual space based on one or more of the translation entries. In some embodiments, the graphics processing circuitry is configured to provide an address for the access to the graphics surface based on translation by the first translation circuitry and second translation circuitry configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface. The disclosed techniques may allow sparse allocation of large graphics surfaces, in various embodiments.


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