The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2020

Filed:

Jan. 30, 2019
Applicant:

Google Llc, Mountain View, CA (US);

Inventors:

Marius Schilder, Mountain View, CA (US);

Timothy Chen, Mountain View, CA (US);

Scott Johnson, Mountain View, CA (US);

Harrison Pham, Mountain View, CA (US);

Derek Martin, Mountain View, CA (US);

Assignee:

Google LLC, Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/57 (2013.01); G06F 21/30 (2013.01); H04L 9/08 (2006.01); G01R 31/317 (2006.01); G06F 21/73 (2013.01); G06F 21/74 (2013.01); G06F 21/75 (2013.01); G06F 21/79 (2013.01); G11C 7/24 (2006.01); G11C 16/22 (2006.01); G11C 29/36 (2006.01); G11C 29/40 (2006.01); G11C 29/46 (2006.01); G01R 31/3185 (2006.01); G11C 17/14 (2006.01); G11C 17/18 (2006.01); G11C 29/04 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G06F 21/57 (2013.01); G01R 31/31719 (2013.01); G01R 31/318588 (2013.01); G06F 21/30 (2013.01); G06F 21/575 (2013.01); G06F 21/73 (2013.01); G06F 21/74 (2013.01); G06F 21/75 (2013.01); G06F 21/79 (2013.01); G11C 7/24 (2013.01); G11C 16/22 (2013.01); G11C 29/36 (2013.01); G11C 29/40 (2013.01); G11C 29/46 (2013.01); H04L 9/0822 (2013.01); H04L 9/0861 (2013.01); G11C 17/14 (2013.01); G11C 17/18 (2013.01); G11C 2029/0401 (2013.01); G11C 2029/0403 (2013.01); G11C 2029/4402 (2013.01);
Abstract

A semiconductor chip device include device state fuses that may be used to configure various device states and corresponding security levels for the semiconductor chip as it transitions from wafer manufacturing to provisioned device. The device states and security levels prevent the semiconductor chip from being accessed and exploited, for example, during manufacturing testing. A secure boot flow process for a semiconductor chip over its lifecycle is also disclosed. The secure boot flow may start at the wafer manufacturing stage and continue on through the insertion of keys and firmware.


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