The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2020

Filed:

May. 23, 2019
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Prashant S. Rawat, San Jose, CA (US);

Shail Aditya Gupta, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/36 (2006.01); G06F 9/50 (2006.01); G06F 15/78 (2006.01); G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
G06F 15/7807 (2013.01); G06F 9/4881 (2013.01);
Abstract

An example method of placing kernels of an application in a data processing engine array (DPE) of a system on chip (SOC) includes obtaining a graph of the application having nodes representing the kernels and edges representing communication between the kernels, sorting the kernels based on runtime ratio associated with each of the kernels, processing the sorted kernels sequentially to place into partitions, determining an execution order of kernels in each of the partitions; and generating implementation data for the SOC for implementing the application therein based on the determined partitions and execution order for each of the partitions.


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